STM32L4R/S Power Supplies
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.
• VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) / 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage. VDDA should be preferably connected to VDD when these peripherals are not used.
• VDD12 = 1.05 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage. VDDUSB should be preferably connected to VDD when the USB is not used. The VDDUSB power supply may not be present as a dedicated pin, but to be internally bonded to VDD. For such devices, VDD has to respect the VDDUSB supply range when the USB is used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (Port G[15:2]). The VDDIO2 voltage level is independent from the VDD voltage and should preferably be connected to VDD when PG[15:2] are not used.
• VDDDSI is an independent DSI power supply dedicated to the DSI regulator and the MIPI DPHY. This supply must be connected to the global VDD.
• VCAPDSI pin is the output of the DSI regulator (1.2 V) which must be connected externally to VDD12DSI.
• VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.
• VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VBAT is internally bonded to VDD for small packages without dedicated pin.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled.
- When VDDA < 2 V, VREF+ must be equal to VDDA.
- When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. VREF+ can be grounded when ADC and DAC are not active. The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register:
- –V REF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
- –V REF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
- VREF- and VREF+ pins are not available on all packages. When not available on the package, they are bonded to VSSA and VDDA, respectively.
- When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to related device datasheet for packages pinout description).
- VREF- must always be equal to VSSA.
An embedded linear voltage regulator is used to supply the internal digital power VCORE. VCORE is the power supply for digital peripherals and memories.
from : RM0432. STM32L4Rxxx and STM32L4Sxxx 페이지 182~
본 글 포함된 상위 정리글
https://igotit.tistory.com/244 의 STM32
첫등록 : 2019년 8월 27일
본 글 단축주소 : https://igotit.tistory.com/2286