- Flash 1024kByte
- RAM 256kByte
Flash - Non-volatile memory
Flash memory is divided into 256 pages of 4 kB each that can be accessed by the CPU via the ICODE and DCODE buses .
Writing to flash memory is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile memory controller.
The CPU can read from flash memory an unlimited number of times, but is restricted in how it writes to flash and the number of writes and erases it can perform.
Flash 관련 정보 명확화.
-플래시 메모리는 Page 로 구분되어있고, nRF52840 의 경우 총 256개의 Page 를 갖고 있다.
- 각 Page의 바이트 사이즈 : 4096Byte .
- 플래시 메모리 총 바이트 사이즈는 Page 수량 * Page 당 바이트 사이즈 = 256 * 4096 이므로 1,048,576 byte.
코드 내에서 플래시 메모리의 Page 수량 과 Page 당 바이트 수 확보하는 방법.
칩의 레지스터 FICR(Factory Information Configuration Registers) 에 해당정보 기록 되어있으며 ,
파일 nRF52840.h 에 #define NRF_FICR 로 정의되어있다.
NRF_FICR->CODEPAGESIZE : 플래시 1개 Page 의 바이트 사이즈 . nRF52840 인 경우 4096 바이트.
NRF_FICR->CODESIZE : 플래시 메모리의 총 Page 수량 . nRF52840 인 경우 256 개.
RAM - Random access memory
The RAM interface is divided into nine RAM AHB slaves.
RAM AHB slaves 0 to 7 are connected to two 4 kB RAM sections each, while RAM AHB slave 8 is connected to six 32 kB sections.
Each RAM section has separate power control for System ON and System OFF mode operation, which is configured via RAM register (see the POWER — Power supply).
NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the UICR (user information configuration registers).
The CONFIG is used to enable the NVMC for writing (CONFIG.WEN = Wen) and erasing (CONFIG.WEN = Een).
The CPU must be halted before initiating a NVMC operation from the debug system.
Writing to flash
When write is enabled, full 32-bit words can be written to word-aligned addresses in flash memory.
The NVMC is only able to write 0 to bits in flash memory that are erased (set to 1). It cannot rewrite a bit back to 1. Only full 32-bit words can be written to flash memory using the NVMC interface. To write less than 32 bits, write the data as a full 32-bit word and set all the bits that should remain unchanged in the word to 1. The restriction on the number of writes (nWRITE) still applies in this case.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
The time it takes to write a word to flash is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash.
NVM writing time can be reduced by using READYNEXT. If this status bit is set to 1, code can perform the next data write to the flash. This write will be buffered and will be taken into account as soon as the ongoing write operation is completed.
Erasing a page in flash
When erase is enabled, the flash memory can be erased page by page using the ERASEPAGE.
After erasing a flash page, all bits in the page are set to 1. The time it takes to erase a page is specified by tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the flash.
See Partial erase of a page in flash for information on dividing the page erase time into shorter chunks.
Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or ERASEALL. The time it takes to write a word to UICR is specified by tWRITE. The CPU is halted if the CPU executes code from the flash while the NVMC is writing to the UICR.
Erasing user information configuration registers (UICR)
When erase is enabled, flash and UICR can be erased completely in one operation by using the ERASEALL. This operation will not erase the factory information configuration registers (FICR).
Access port protection behavior
When access port protection is enabled, parts of the NVMC functionality will be blocked in order to prevent intentional or unintentional erase of UICR.
Partial erase of a page in flash
Partial erase is a feature in the NVMC to split a page erase time into shorter chunks to prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in flash memory and does not work with UICR.
When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG. A flash page is erased when its erase time reaches tERASEPAGE. Use ERASEPAGEPARTIAL N number of times so that N * ERASEPAGEPARTIALCFG ≥ tERASEPAGE, where N * ERASEPAGEPARTIALCFG gives the cumulative (total) erase time. Every time the cumulative erase time reaches tERASEPAGE, it counts as one erase cycle.
After the erase is complete, all bits in the page are set to 1. The CPU is halted if the CPU executes code from the flash while the NVMC performs the partial erase operation.
The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started but the total erase time is less than tERASEPAGE.
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states for a cache miss, where the instruction is not available in the cache and needs to be fetched from flash, is shown in CPU.
Enabling the cache can increase CPU performance and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will decrease.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every instruction cache hit or miss, respectively. The hit and miss profiling registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers.
SoftDevice 사용하는 경우 플래시 지우기, 읽기
SoftDevice 사용하는 경우에는 NVMC 활용하여 플래시 지우기, 읽기 안되며, SoftDevice 에서 제공하는 함수 이용해야 함.
첫 등록 : 2023.02.09
최종 수정 : 2023.07.24
단축 주소 : https://igotit.tistory.com/4230